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INTEGRATED CIRCUITS
FB2031 9-bit latched/registered/pass-thru Futurebus+ transceiver
Product specification IC19 Data Handbook 1995 May 25
Philips Semiconductors
Philips Semiconductors
Product specification
9-bit latched/registered/pass-thru Futurebus+ transceiver
FB2031
FEATURES
* Latched, registered or straight through in
either A to B or B to A path
* Reduced BTL voltage swing produces less
noise and reduces power consumption
* Controlled output ramp and multiple GND
pins minimize ground bounce
* Drives heavily loaded backplanes with
equivalent load impedances down to 10.
* Built-in precision band-gap reference
provides accurate receiver thresholds and improved noise immunity
* High drive 100mA BTL open collector
drivers on B-port
* Compatible with IEEE Futurebus+ or
proprietary BTL backplanes
* Allows incident wave switching in heavily
loaded backplane buses
* Each BTL driver has a dedicated Bus GND
for a signal return
* Glitch-free power up/power down operation * Low ICC current * Tight output skew * Supports live insertion
QUICK REFERENCE DATA
SYMBOL tPLH tPHL tPLH tPHL CO IOL Propagation delay An to Bn Propagation delay Bn to An Output capacitance (B0 - Bn only) Output current (B0 - Bn only) AIn to Bn (outputs Low or High) ICC Supply current S l t Bn to AOn (outputs Low) Bn to AOn (outputs High) PARAMETER TYPICAL 2.7 4.4 4.2 6 100 17 50 25 UNIT ns ns pF mA mA mA
ORDERING INFORMATION
PACKAGE 52-pin Plastic Quad Flat Pack (QFP) COMMERCIAL RANGE VCC = 5V10%; Tamb = 0C to +70C FB2031BB INDUSTRIAL RANGE VCC = 5V10%; Tamb = -40C to +85C CD3206BB DRAWING NUMBER SOT379-1
PIN CONFIGURATION
LOGIC GND TCK (option) TMS (option) BUS GND BIAS V
OEB0
OEB1
OEA
VCC
A1
A0
VCC
52 51 50 49 48 47 46 45 44 43 42 41 40 LOGIC GND A2 LOGIC GND A3 LOGIC GND A4 LOGIC GND A5 LOGIC GND A6 LOGIC GND A7 LOGIC GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A8 SEL1 16 17 18 19 20 21 22 23 24 25 26 TDI (option) TDO (option) BUS GND BG GND BG VCC LCBA LCAB SEL0 VCC B8 B7 39 38 37 36 BUS GND B1 BUS GND B2 BUS GND B3 BUS GND B4 BUS GND B5 BUS GND B6 BUS GND
9-Bit latched/registered transceiver FB2031
B0 35 34 33 32 31 30 29 28 27
52-lead PQFP
SG00060
1995 May 25
2
853-1714 15279
Philips Semiconductors
Product specification
9-bit latched/registered/pass-thru Futurebus+ transceiver
FB2031
DESCRIPTION
The FB2031 is a 9-bit latched/registered transceiver featuring a latched, registered or pass-thru mode in either the A-to-B or B-to-A direction. The FB2031 is intended to provide the electrical interface to a high performance wired-OR bus. The TTL-level side (A port) has a common I/O. The common I/O, open collector B port operates at BTL signal levels. The logic element for data flow in each direction is controlled by two mode select inputs (SEL0 and SEL1). A "00" configures latches in both directions. A "10" configures thru mode in both directions. A "01" configures register mode in both directions. A "11" configures register mode in the A-to-B direction and latch mode in the B-to-A direction. When configured in the buffer mode, the inverse of the input data appears at the output port. In the register mode, data is stored on the rising edge of the appropriate clock input (LCAB or LCBA). In the latch mode, clock pins serve as transparent-Low latch enables. Regardless of the mode, data is inverted from input to output. The 3-State A port is enabled by asserting a High level on OEA. The B port has two output enables, OEB0 and OEB1. Only when OEB0 is High and OEB1 is Low is the output enabled.
When either OEB0 is Low or OEB1 is High, the B port is inactive and is pulled to the level of the pullup voltage. New data can be entered in the register and latched modes or can be retained while the associated outputs are in 3-State (A port) or inactive (B port). The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port insure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V. The B-port interfaces to "Backplane Transceiver Logic" (see the IEEE 1194.1 BTL standard). BTL features low power consumption by reducing voltage swing (1V p-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes. Output clamps are provided on the BTL outputs to further reduce switching noise. The "VOH" clamp reduces inductive ringing effects during a Low-to-High transition. The "VOH" clamp is always active. The other clamp, the "trapped reflection" clamp, clamps out ringing below the BTL 0.5V VOL level. This clamp remains active for approximately 100ns after a High-to-Low transition.
To support live insertion, OEB0 is held Low during power on/off cycles to insure glitchfree B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 5V level while VCC is Low. The BIAS V pin is a low current input which will reverse-bias the BTL driver series Schottky diode, and also bias the B port output pins to a voltage between 1.62V and 2.1V. This bias function is in accordance with IEEE BTL Standard 1194.1. If live insertion is not a requirement, the BIAS V pin should be tied to a VCC pin. The LOGIC GND and BUS GND pins are isolated inside the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package. Each BTL driver has an associated BUS GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a "hard" signal failure occurs instead of a pattern dependent error that may be infrequent and impossible to troubleshoot. As with any high power device, thermal considerations are critical. It is recommended that airflow (300Ifpm) and/or thermal mounting be used to ensure proper junction temperature.
PACKAGE THERMAL CHARACTERISTICS
PARAMETER ja ja jc CONDITION Still air 300 Linear feet per minute air flow Thermally mounted on one side to heat sink 52-PIN PLASTIC QFP 80C/W 58C/W 20C/W
PIN DESCRIPTION
SYMBOL A0 - A8 B0 - B8 OEB0 OEB1 OEA BUS GND LOGIC GND VCC BIAS V BG VCC BG GND SEL0 SEL1 LCAB LCBA TMS TCK TDI TDO PIN NUMBER 50, 52, 2, 4, 6, 8, 10, 12, 14 40, 38, 36, 34, 32, 30, 28, 26, 24 46 45 47 25, 27, 29, 31, 33, 35, 37, 39, 41 51, 1, 3, 5, 7, 9, 11, 13 23, 43, 49 48 17 19 20 15 18 16 42 44 22 21 TYPE I/O I/O Input Input Input GND GND Power Power Power GND Input Input Input Input Input Input Input Output NAME AND FUNCTION BiCMOS data inputs/3-State outputs (TTL) Data inputs/Open Collector outputs, High current drive (BTL) Enables the B outputs when High Enables the B outputs when Low Enables the A outputs when High Bus ground (0V) Logic ground (0V) Positive supply voltage Live insertion pre-bias pin Band Gap threshold voltage reference Band Gap threshold voltage reference ground Mode select Mode select A to B clock/latch enable (transparent latch when Low) B to A clock/latch enable (transparent latch when Low) Test Mode Select (optional, if not implemented then no connect) Test Clock (optional, if not implemented then no connect) Test Data In (optional, if not implemented then no connect) Test Data Out (optional, if not implemented then shorted to TDI)
1995 May 25
3
Philips Semiconductors
Product specification
9-bit latched/registered/pass-thru Futurebus+ transceiver
FB2031
FUNCTION TABLE
MODE An to Bn thru mode An to Bn transparent latch An to Bn latch and read Bn outputs latched and read (preconditioned latch) An to Bn register Bn to An thru mode INPUTS An L H L H l h X l h -- -- -- Bn to An transparent latch -- -- -- -- Bn to An latch and read -- -- -- An outputs latched and read (preconditioned latch) -- -- -- -- X X X Bn* -- -- -- -- -- -- -- -- -- L H L H L H l h l h X X l h X X X OEB0 H H H H H H H H H Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable X X X X OEB1 L L L L L L L L L OEA L L L L L L X L L H H H H H H H H H H H H H H X X L LCAB X X L L H X X X X X X X X X X X X X X X X X LCBA X X X X X X X X X X X L L L L H H X X X SEL0 H H L L L L L X X H H L L H H L L H H L H L L X X X SEL1 L L L L L L L H H L L L L H H L L H H L H H H X X X OUTPUTS An input input input input input input X input input H L H L H L H L H L latched data latched data H L X X Z Bn H** L H** L H** L latched data H** L input input input input input input input input input input X X input input H** H** X
Bn to An register Disable Bn outputs Disable An outputs
Disable Disable L X X X H X
FUNCTION SELECT TABLE
MODE SELECTED Thru mode Register mode (An to Bn) Latch mode (An to Bn) Register mode (Bn to An) Latch mode (Bn to An) NOTES: H = High voltage level L = Low voltage level l = Low voltage level one set-up time prior to the Low-to-High LCXX transition h = High voltage level one set-up time prior to the Low-to-High LCXX transition SEL0 H X L L L H X Z -- H** = = = = = Don't care High-impedance (OFF) state Input not externally driven Low-to-High transition Goes to level of pull-up voltage SEL1 L H L H L H Bn* = Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state. Disable = OEB0 is Low or OEB1 is High.
1995 May 25
4
Philips Semiconductors
Product specification
9-bit latched/registered/pass-thru Futurebus+ transceiver
FB2031
LOGIC DIAGRAM
OEB0 OEB1 OEA 46 45 47 D E D A8 14 Clk Q MUX A B 24 B8 Q
MUX A B
Q Q
D D E
D E D A7 12 10 Clk
Q
Q
D Clk
Q
MUX A B
26 28 30
B7
MUX 8 6 D 4 2 E D Clk A1 52 Q MUX A B Q A B
Q
D E 32 34 36 38 B1
BTL
TTL
Q
D Clk
MUX A B
Q
D E
D E D Clk A0 50
Q
Q
D Clk
Q MUX A B
40
B0
MUX A B
Q
D E
Q LCAB SEL0 SEL1 LCBA 18 20 15 16 Decode In Out
D Clk
TMS TCK TDI TDO
42 44 22 21
(JTAG Boundary Scan pins)
LOGIC GND BUS GND BIAS V VCC BG VCC BG GND
= = = = = =
1, 3, 5, 7, 9, 11, 13, 51 25, 27, 29, 31, 33, 35, 37, 39, 41 48 23, 43, 49 17 19 SG00061
1995 May 25
5
Philips Semiconductors
Product specification
9-bit latched/registered/pass-thru Futurebus+ transceiver
FB2031
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range. SYMBOL VCC VIN IIN VOUT IOUT TSTG Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Storage temperature A0 - A8 B0 - B8 All inputs except B0 - B8 B0 - B8 PARAMETER RATING -0.5 to +7.0 -1.2 to +7.0 -1.2 to +3.5 -40 to +5.0 -0.5 to +VCC 48 200 -65 to +150 C mA V mA UNIT V V
RECOMMENDED OPERATING CONDITIONS (Industrial)
SYMBOL VCC VIH VIL IIK IOH IOL IIA COB Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Off device input current Output capacitance of B port Operating free-air temperature range -40 Except B0-B8 B0 - B8 Except B0 - B8 B0 - B8 Control inputs B0 - B8 & A0 - A8 A0 - A8 A0 - A8 B0 - B8 Except B0 - B8, VI = 0 to 5.5V, VCC = 0V 6 PARAMETER MIN 4.5 2.0 1.62 1.55 0.8 1.47 -40 -18 -3 24 100 100 7 +85 A pF C mA mA mA V LIMITS TYP 5.0 MAX 5.5 V V UNIT
RECOMMENDED OPERATING CONDITIONS (Commercial)
SYMBOL VCC VIH VIL IIK IOH IOL IIA COB Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Off device input current Output capacitance of B port Operating free-air temperature range 0 Except B0-B8 B0 - B8 Except B0 - B8 B0 - B8 Control inputs B0 - B8 & A0 - A8 A0 - A8 A0 - A8 B0 - B8 Except B0 - B8, VI = 0 to 5.5V, VCC = 0V 6 PARAMETER MIN 4.5 2.0 1.62 1.55 0.8 1.47 -40 -18 -3 24 100 100 7 +70 A pF C mA mA mA V LIMITS TYP 5.0 MAX 5.5 V V UNIT
1995 May 25
6
Philips Semiconductors
Product specification
9-bit latched/registered/pass-thru Futurebus+ transceiver
FB2031
DC ELECTRICAL CHARACTERISTICS (Industrial)
Over recommended operating free-air temperature range unless otherwise noted. SYMBOL IOH IOFF VOH PARAMETER High level output current Power-off output current High-level output voltage B0 - B8 B0 - B8 A0 - A8 4 A0 - A8 4 VOL Low-level output voltage B0 - B8 TEST CONDITIONS1 MIN VCC = MAX, VIL = MAX, VIH = MIN, VOH = 1.9V VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 1.9V VCC = MIN, VIL = MAX, VIH = MIN, IOH = -24mA VCC = MIN, VIL = MAX, VIH = MIN, IOH = -3mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 24mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 80mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 100mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 80mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 4mA VIK Input clamp voltage Control pins A0 - A8 B0 - Bn II Input current at maximum input voltage High-level input current Except B0-B8 Except B0-B8 B0 - B8 Except B0-B8 B0 - B8 IIH + IOZH IIL + IOZL IOS Off-state I/O High current Off-state I/O Low current Short-circuit output current 3 A0 - A8 A0 - A8 A0 - A8 only An to Bn Bn to An ICC Supply current (total) Bn to An ICCZ Worst case VCC = MIN, II = IIK VCC = MIN, II = -18mA VCC = MAX, VI = 0.5V or 5.5V VCC = MAX, VI = 2.7V VCC = MAX, VI = 1.9V VCC = MAX, VI = 3.5V 5 VCC = MAX, VI = 0.5V VCC = MAX, VI = 0.75V VCC = MAX, VO = 2.7V VCC = MAX, VO = 0.5V VCC = MAX, VO = 0.0V VCC = MAX, outputs Low or High VCC = MAX, outputs Low VCC = MAX, outputs High VCC = MAX, outputs 3-State VCC = MAX, all A and B outputs on -45 17 50 25 28 50 IIL Low-level input current 100 -20 -100 50 -50 -150 30 78 45 50 78 mA A A mA 0.5 -0.5 -1.2 50 20 100 mA A V A A .75 1.0 2.0 2.5 2.85 0.5 1.1 1.15 1.15 V LIMITS TYP2 MAX 100 200 A A V UNIT
IIH
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side. 5. For B port input voltage between 3 and 5 volts IIH will be greater than 100A, but the parts will continue to function normally. 6. B0 - B8 clamps remain active for a minimum of 80ns following a High-to-Low transition. 7. Temperature range: 0 to +85C. 8. Temperature range: -40 to 0C.
1995 May 25
7
Philips Semiconductors
Product specification
9-bit latched/registered/pass-thru Futurebus+ transceiver
FB2031
DC ELECTRICAL CHARACTERISTICS (Commercial)
Over recommended operating free-air temperature range unless otherwise noted. SYMBOL IOH IOFF VO OH PARAMETER High level output current Power-off output current High-level High level output voltage B0 - B8 B0 - B8 A0 - A8 4 A0 - A8 4 VO OL Low-level Low level output voltage B0 - B8 Control pins VIK II Input clamp voltage Input current at maximum input voltage A0 - A8 B0 - Bn Except B0-B8 Except B0-B8 IIH Hi h l l input current t t High-level i B0 - B8 Except B0-B8 B0 - B8 IIH + IOZH IIL + IOZL IOS Off-state I/O High current Off-state I/O Low current Short-circuit output current 3 A0 - A8 A0 - A8 A0 - A8 only An to Bn Bn to An ICC Supply current (total) Bn to An ICCZ Worst case TEST CONDITIONS1 VCC = MAX, VIL = MAX, VIH = MIN, VOH = 1.9V VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 1.9V VCC = MIN, VIL = MAX, VIH = MIN, IOH = -24mA VCC = MIN, VIL = MAX, VIH = MIN, IOH = -3mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 24mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 80mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 100mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 4mA VCC = MIN, II = IIK VCC = MIN, II = -18mA VCC = MAX, VI = 0.0V or 5.5V VCC = MAX, VI = 2.7V VCC = MAX, VI = 1.9V VCC = MAX, VI = 3.5V 5 VCC = MAX, VI = 0.5V VCC = MAX, VI = 0.75V VCC = MAX, VO = 2.7V VCC = MAX, VO = 0.5V VCC = MAX, VO = 0.0V VCC = MAX, outputs Low or High VCC = MAX, outputs Low VCC = MAX, outputs High VCC = MAX, outputs 3-State VCC = MAX, all A and B outputs on -45 17 50 25 28 50 100 -20 -100 50 -50 -150 30 78 45 50 78 mA A A mA 0.5 -0.5 -1.2 50 20 100 A mA A V A .75 1.0 2.0 2.5 2.85 0.5 1.1 1.15 V LIMITS MIN TYP2 MAX 100 100 UNIT A A V
IIL
Low-level input current
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side. 5. For B port input voltage between 3 and 5 volts IIH will be greater than 100A, but the parts will continue to function normally. 6. B0 - B8 clamps remain active for a minimum of 80ns following a High-to-Low transition.
1995 May 25
8
Philips Semiconductors
Product specification
9-bit latched/registered/pass-thru Futurebus+ transceiver
FB2031
LIVE INSERTION SPECIFICATIONS
SYMBOL VBIASV IBIASV VBn ILM IHM IBnPEAK IOLOFF tGR Bias pin voltage Bias pin DC current in PARAMETER VCC = 0 to 5.25V, Bn = 0 to 2.0V VCC = 0 to 4.75V, Bn = 0 to 2.0V, Bias V = 4.5 to 5.5V VCC = 4.5 to 5.5V, Bn = 0 to 2.0V, Bias V = 4.5 to 5.5V B0 - B8 = 0V, Bias V = 5.0V B0 - B8 = 2V, Bias V = 4.5 to 5.5V B0 - B8 = 1V, Bias V = 4.5 to 5.5V VCC = 0 to 5.25V, B0 - B8 = 0 to 2.0V, Bias V = 4.5 to 5.5V, OEB0 = 0.8V, tr = 2ns VCC = 0 to 5.25V, OEB0 = 0.8V VCC = 0 to 2.2V, OEB0 = 0 to 5V VCC = 5.0V 1.35 1.62 1 -1 10 100 100 1.0 LIMITS MIN 4.5 NOM MAX 5.5 1 10 2.1 UNIT V mA A V A A mA A ns
Bus voltage during prebias Fall current during prebias Rise current during prebias Peak bus current during insertion Power up current u Input glitch rejection
AC ELECTRICAL CHARACTERISTICS (Industrial)
A PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C, VCC = 5V, CL = 50pF, RL = 500 MIN fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tTLH tTHL tSK(o) tSK(p) Maximum clock frequency Propagation delay (thru mode) Bn to An Propagation delay (transparent latch) Bn to An Propagation delay LCBA to An Propagation delay SEL0 or SEL1 to An Output enable time from High or Low OEA to An Output disable time to High or Low OEA to An Output transition time, An Port 10% to 90%, 90% to 10% Output to output skew for multiple channels1 Pulse skew tPHL - tPLH MAX
2
Tamb = -40 to +85C, VCC = 5V10%, CL = 50pF, RL = 500 MIN 100 2.3 2.4 2.7 2.5 2.0 2.0 1.2 1.5 1.8 1.7 1.6 1.5 3.0 1.7 MAX
UNIT
TYP 150 4.4 4.2 4.6 4.3 4.1 4.7 3.8 3.9 3.5 3.8 3.4 3.2
MAX 5.9 5.5 6.2 5.9 5.5 6.1 5.2 6.0 4.8 5.3 4.8 4.8
Waveform 4 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 5, 6 Waveform 5, 6 Test Circuit and Waveforms Waveform 3 Waveform 2
120 2.5 2.4 2.9 2.8 2.6 2.4 1.5 1.7 2.1 2.0 1.9 1.7
MHz 7.0 6.2 7.1 7.0 6.2 6.8 6.2 6.5 6.0 6.3 5.5 5.5 7.5 4.0 1.5 1.0 ns ns ns ns ns ns ns ns ns
0.5 0.5
1.0 1.0
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side. 5. For B port input voltage between 3 and 5 volts IIH will be greater than 100A, but the parts will continue to function normally. 6. B0 - B8 clamps remain active for a minimum of 80ns following a High-to-Low transition.
1995 May 25
9
Philips Semiconductors
Product specification
9-bit latched/registered/pass-thru Futurebus+ transceiver
FB2031
AC ELECTRICAL CHARACTERISTICS (Industrial)
B PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C, VCC = 5V, CD = 30pF, RU = 16.5 MIN tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tTLH tTHL tSK(o) tSK(p) Propagation delay (thru mode) An to Bn Propagation delay (transparent latch) An to Bn Propagation delay LCAB to Bn Propagation delay SEL0 or SEL1 to Bn Enable/disable time OEB0 or OEB1 to Bn Output transition time, Bn Port (1.3V to 1.8V) Output to output skew for multiple channels1 Pulse tPHL - tPLH MAX skew2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Test Circuit and Waveforms Waveform 3 Waveform 2 1.0 1.0 1.0 1.0 2.0 1.5 2.0 1.5 1.5 1.2 1.0 0.6 1.0 0.4 0.3 1.0 TYP 3.0 2.7 3.2 3.1 4.0 4.0 3.5 2.3 3.0 2.4 MAX 5.0 4.0 5.0 4.2 5.5 5.5 5.5 4.5 5.0 4.5 2.0 3.0 Tamb = -40 to +85C, VCC = 5V10%, CD = 30pF, RU = 16.5 MIN 1.5 1.5 1.5 1.5 1.5 1.5 2.0 1.0 1.0 1.0 0.9 0.6 1.6 MAX 5.7 4.5 5.5 5.0 6.5 6.0 6.1 5.5 5.7 5.5 3.0 3.0 1.6 1.5 ns ns ns ns ns ns ns ns UNIT
NOTES: 1. tPNactual - tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). 2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).
1995 May 25
10
Philips Semiconductors
Product specification
9-bit latched/registered/pass-thru Futurebus+ transceiver
FB2031
AC ELECTRICAL CHARACTERISTICS (Commercial)
A PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C, VCC = 5V, CL = 50pF, RL = 500 MIN fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tTLH tTHL tSK(o) tSK(p) Maximum clock frequency Propagation delay (thru mode) Bn to An Propagation delay (transparent latch) Bn to An Propagation delay LCBA to An Propagation delay SEL0 or SEL1 to An Output enable time from High or Low OEA to An Output disable time to High or Low OEA to An Output transition time, An Port 10% to 90%, 90% to 10% Output to output skew for multiple channels1 Pulse skew 2 tPHL - tPLH MAX Waveform 4 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 5, 6 Waveform 5, 6 Test Circuit and Waveforms Waveform 3 Waveform 2 0.5 0.5 1.0 1.0 120 2.5 2.4 2.9 2.8 2.6 2.4 1.5 1.7 2.1 2.0 1.9 1.7 TYP 150 4.4 4.2 4.6 4.3 4.1 4.7 3.8 3.9 3.5 3.8 3.4 3.2 5.9 5.5 6.2 5.9 5.5 6.1 5.2 6.0 4.8 5.3 4.8 4.8 MAX Tamb = 0 to +70C, VCC = 5V10%, CL = 50pF, RL = 500 MIN 100 2.3 2.4 2.7 2.5 2.0 2.0 1.2 1.5 1.8 1.7 1.6 1.5 2.0 1.0 6.6 5.9 7.0 6.5 6.0 6.5 6.0 6.5 5.8 6.0 5.4 5.4 7.5 3.5 1.5 1.0 MAX MHz ns ns ns ns ns ns ns ns ns UNIT
NOTES: 1. tPNactual - tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). 2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).
1995 May 25
11
Philips Semiconductors
Product specification
9-bit latched/registered/pass-thru Futurebus+ transceiver
FB2031
AC ELECTRICAL CHARACTERISTICS (Commercial)
B PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C, VCC = 5V, CD = 30pF, RU = 16.5 MIN tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tTLH tTHL tSK(o) tSK(p) Propagation delay (thru mode) An to Bn Propagation delay (transparent latch) An to Bn Propagation delay LCAB to Bn Propagation delay SEL0 or SEL1 to Bn Enable/disable time OEB0 or OEB1 to Bn Output transition time, Bn Port (1.3V to 1.8V) Output to output skew for multiple channels1 Pulse tPHL - tPLH MAX skew2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Waveform 1, 2 Test Circuit and Waveforms Waveform 3 Waveform 2 1.0 1.0 1.0 1.0 2.0 1.5 2.0 1.5 1.5 1.5 1.0 0.6 0.4 0.3 TYP 3.0 2.7 3.2 3.1 4.0 4.0 3.5 2.3 3.0 2.4 MAX 5.0 4.0 5.0 4.2 5.5 5.5 5.5 4.5 5.0 4.5 2.0 3.0 1.0 1.0 Tamb = 0 to +70C, VCC = 5V10%, CD = 30pF, RU = 16.5 MIN 1.0 0.5 1.0 0.8 1.5 1.0 2.0 1.0 1.0 0.8 1.0 0.6 MAX 5.5 4.5 5.5 4.5 6.0 6.0 6.0 5.0 5.5 5.5 2.3 2.3 1.6 1.5 ns ns ns ns ns ns ns ns UNIT
NOTES: 1. tPNactual - tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). 2. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).
AC SETUP REQUIREMENTS (Industrial)
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C, VCC = 5V, Tamb = -40 to +85C, VCC = 5V10%, UNIT
CL = 50pF (A side) / CD = 30pF (B side) RL = 500 (A side) / RU = 16.5 (B side) MIN ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) Setup time An to LCAB Hold time An to LCAB Setup time Bn to LCBA Hold time Bn to LCBA Pulse width, High or Low LCAB or LCBA Waveform 4 Waveform 4 Waveform 4 Waveform 4 Waveform 4 1.0 1.0 1.0 1.0 2.0 2.0 0.0 0.0 3.0 3.0 TYP MAX MIN 1.5 1.0 2.0 1.0 3.0 3.0 0.0 0.0 3.0 3.0 MAX ns ns ns ns ns
1995 May 25
12
Philips Semiconductors
Product specification
9-bit latched/registered/pass-thru Futurebus+ transceiver
FB2031
AC SETUP REQUIREMENTS (Commercial)
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C, VCC = 5V, Tamb = 0 to +70C, VCC = 5V10%, UNIT
CL = 50pF (A side) / CD = 30pF (B side) RL = 500 (A side) / RU = 16.5 (B side) MIN ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) Setup time An to LCAB Hold time An to LCAB Setup time Bn to LCBA Hold time Bn to LCBA Pulse width, High or Low LCAB or LCBA Waveform 4 Waveform 4 Waveform 4 Waveform 4 Waveform 4 1.0 1.0 1.0 1.0 2.0 2.0 0.0 0.0 3.0 3.0 TYP MAX MIN 1.5 1.0 2.0 1.0 3.0 3.0 0.0 0.0 3.0 3.0 MAX ns ns ns ns ns
1995 May 25
13
Philips Semiconductors
Product specification
9-bit latched/registered/pass-thru Futurebus+ transceiver
FB2031
AC WAVEFORMS
Input VM tPLH Output VM VM tPHL VM Output Input VM tw (input) tPHL VM VM tPLH tw (output) VM
Waveform 1. Propagation Delay for Data or Output Enable to Output
Waveform 2. Propagation Delay for Data or Output Enable to Output
An, Bn
VM tSK(o)
An, Bn
An, Bn
VM
LCAB, LCBA
Waveform 3. Output to Output Skew
VM tPZH An VM VM tPHZ VOH -0.3V OV
Waveform 4. Setup and Hold Times, Pulse Widths and Maximum Frequency
OEA VM tPZL An VM VM tPLZ VOL +0.3V
OEA
Waveform 5. 3-State Output Enable Time to High Level and Output Disable Time from High Level
Waveform 6. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
SG00062
NOTE: VM = 1.55V for Bn, VM = 1.5V for all others. The shaded areas indicate when the input is permitted to change for predictable output performance.
1995 May 25
14
II IIIIII II IIIIII
VM
ts
th
VM
ts tw(L)
th
tw(H)
VM
1/fMAX
Philips Semiconductors
Product specification
9-bit latched/registered/pass-thru Futurebus+ transceiver
FB2031
TEST CIRCUIT AND WAVEFORMS
VCC 7.0V RL NEGATIVE PULSE 90% VM 10% tTHL CL RL tW VM 10% LOW V tTLH 90% AMP (V)
VIN PULSE GENERATOR RT D.U.T.
VOUT
(tf) (tr)
90% VM tW
(tr) (tf)
AMP (V)
tTLH 90% POSITIVE PULSE VM 10%
tTHL
Test Circuit for 3-State Outputs on A Port SWITCH POSITION TEST tPLZ, tPZL All other SWITCH closed open
VCC BIAS V VIN PULSE GENERATOR RT D.U.T. 2.0V (for RU = 9 ) 2.1V (for RU = 16.5 )
10%
LOW V
VM = 1.55V for Bn, VM = 1.5V for all others.
Input Pulse Definitions Family FB+ A Port B Port INPUT PULSE REQUIREMENTS Amplitude 3.0V 2.0V Low V 0.0V 1.0V Rep. Rate 1MHz 1MHz tW tTLH tTHL 2.5ns 2.0ns
500ns 2.5ns 500ns 2.0ns
VOUT
RU
CD
Test Circuit for Outputs on B Port
DEFINITIONS: RL = Load Resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. CD = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RU = Pull up resistor; see AC CHARACTERISTICS for value.
SG00063
1995 May 25
15
Philips Semiconductors
Product specification
9-bit latched/registered/pass-thru Futurebus+ transceiver
FB2031
QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm
SOT379-1
1995 May 25
16
Philips Semiconductors
Product specification
9-bit latched/registered/pass-thru Futurebus+ transceiver
FB2031
NOTES
1995 May 25
17
Philips Semiconductors
Product specification
9-bit latched/registered/pass-thru Futurebus+ transceiver
FB2031
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 01-0006835 9397 750
Philips Semiconductors
1995 May 25 18

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